Low-Capacitance ESD Protection for High-Speed Circuits and Systems addresses the critical challenge of safeguarding multi-gigabit integrated circuits against Electrostatic Discharge without compromising signal integrity. As operational frequencies rise, standard protection devices introduce parasitic capacitance that degrades high-speed performance. This talk explores advanced ESD topologies, device physics, layout optimizations, and co-design strategies to ensure robust ESD immunity while minimizing parasitic loading.

Chun-Yu Lin received the Ph.D. degree from the Institute of Electronics, National Chiao Tung University, Taiwan, in 2009. He was the Assistant Professor from 2013 to 2017, Associate Professor from 2017 to 2021, and Distinguished Professor from 2021 to 2024, at the Department of Electrical Engineering, National Taiwan Normal University. Starting from 2024, he relocates to join the Institute of Electronics at National Yang Ming Chiao Tung University. Now, he also serves as the President of Taiwan ESD Association. He authored or co-authored more than 100 conference and journal publications. His current research interests include ESD protection designs and biomimetic circuit designs.

The rapid growth of electric mobility, renewable energy, industrial automation, and high-efficiency power conversion is driving development of next-generation power semiconductors with higher voltage capability, lower losses, faster switching, and enhanced reliability. While Si IGBTs and MOSFETs remain central to high-power applications, wide-bandgap technologies such as 4H-SiC and GaN are opening new opportunities for high-frequency, high-power conversion. Taking a device-to-driver perspective, this work examines the co-design of next-generation power devices and their gate-driver ICs. The evolution from Si to advanced 4H-SiC MOSFETs and IGBTs is discussed through material properties, device architecture, breakdown capability, conduction, switching performance, and reliability. Particular emphasis is placed on the power device–driver interface: gate-drive optimization, switching dynamics, parasitics, dv/dt and di/dt control, short-circuit protection, active gate driving, EMI, and thermal management. Joint optimization of device and driver characteristics is shown to enable higher efficiency, reliability, switching speed, and power density. The discussion closes with emerging directions — intelligent power devices, integrated sensing and protection, and optimized device-to-driver platforms — for EVs, renewable energy, industrial drives, data centers, and future power-electronics systems.

Dr. Soumyaranjan Routray received his Ph.D. from National Institute of Technology Silchar, India, under the Visvesvaraya PhD Scheme, MeitY, Government of India, in 2018. He is currently a Research Assistant Professor (RAP) in the Department of Electronics and Communication Engineering at SRM Institute of Science and Technology, Kattankulathur, Chennai, India, and a Senior Member of the IEEE Electron Devices Society. His current research interests include semiconductor devices such as power devices, solar cells, memristor design, low-cost sensors, and high-performance transistors. He also has expertise in computer-aided design (CAD) tools for III-Nitride semiconductor qubit design. Dr. Routray has contributed more than 70 articles to leading international journals and conferences, including Solar Energy, Applied Physics Letters, IEEE Sensors Journal, IEEE TNANO, IEEE TED, IEEE Journal of Quantum Electronics, Solid-State Electronics, and Semiconductor Science and Technology, among others. He is a five-time recipient of the IEEE Publication Award in India and currently serves as a Guest Editor for the Nanomaterials journal.

Traditional aquaculture relies heavily on intuition, hampered by turbid water and unpredictable biological variables. Mirroring semiconductor manufacturing—where rigid process control replaces empirical guesswork—this talk presents how integrating IC technologies, IoT, and AI converts aquaculture into a data-driven "biological growth management".

Addressing the need of smart shrimp farming, we detail an end-to-end system architecture engineered to overcome severe field constraints like limited bandwidth, power, and latency. Underwater imaging devices pair with smart edge and cloud platforms to perform localized image enhancement, object detection, and feed tracking. Transmitting only secure, lightweight inference information allows entry-level desktop servers to sustain real-time analytics across over multiple concurrent video streams. AI models deliver 24/7 biological monitoring (estimating size, count, and health), capturing 300x more growth data than manual sampling with a tight 4.5% error margin.

We have demonstrated a 26% yield increase, a 22% higher survival rate, and a 6% reduction in the Feed Conversion Ratio (FCR) with our system. An FPGA prototyping and test chip for LLM-based SoC are under way. This presentation offers key takeaways for computer scientists and IC designers on hardware-software co-design, edge acceleration, and cloud scalability in dynamic biological environments.

Ing-Jer Huang is an ASE chair professor in the Department of Computer Science and Engineering at National Sun Yat-Sen University in Taiwan. His research areas include computer architecture, embedded systems, IC design, artificial intelligence and internet-of-things. Many of his work have been licensed to IC related companies. He’s also contributed to socially impactful efforts, such as smart aquaculture farming systems, wearable tech for elder care, and a TV documentary series in computer technologies. His interdisciplinary enthusiasm has received technical awards such as National Invention Award 2014, FutureTech Awards 2018/2021, National Innovation Award 2022/2023, and APICTA Award 2023, and a Houston International Film Festival Award, 2019 for his TV series on computer education.